Additional Materials
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Relevant Publications
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Asynchronous Design Review
- S. Nowick and M. Singh, Asynchronous Design - Part 1: Overview and Recent Advances
, IEEE Design and Test, Volume 32, Issue 3, pp. 5-18, June 2015.
- S. Nowick and M. Singh, Asynchronous Design - Part 2: Systems and Methodologies , IEEE Design and Test, Volume 32, Issue 3, pp. 19-28, June 2015.
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Latch Controllers and Template-based Design
- I. Sutherland, Micropipelines , Communications of the ACM, Volume 32, Issue 6, pp. 720-738, June 1989
- M. Singh and S. Nowick, MOUSETRAP: High-Speed Transition Signaling Asynchronous Pipelines , IEEE Transactions on VLSI Systems, Volume 15, Issue 6, pp. 684-698, June 2007.
- Modular Design of Asynchronous Circuits Defined by Graphs, , IEEE Transactions on Computers, Volume C-26, No. 8, 1977.
- L. Hollaar, Direct Implementation of Asynchronous Control Units , IEEE Transactions on Computers, Volume C-31, Issue 12, pp. 1133-1141, 1982.
- Christos P. Sotiriou, Implementing Asynchronous Circuits using a Conventional EDA Tool-Flow , Proceedings of 39th DAC, pp. 415-418, 2002.
- Four-Phase Micropipeline Latch Control Circuits, Four-Phase Micropipeline Latch Control Circuits , IEEE Transactions on VLSI Systems, Volume 4, Issue 2, pp. 247-253, 1996.
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De-Synchronisation
- I. Blunno, J. Cortadella, A. Kondratyev, L. Lavagno, K. Lwin and C. Sotiriou, Handshake Protocols for De-synchronization , Proceedings of the 10th International Symposium on Asynchronous Circuits and Systems, pp. 149-158, 2004.
- J. Cortadella, A. Kondratyev, L. Lavagno and C. P. Sotiriou, Desynchronization: Synthesis of Asynchronous Circuits from Synchronous Specifications , IEEE Transactions on CAD, Volume 25, No. 10, pp 1904-1921, 2006.
- N. Penmetsa, C. P. Sotiriou and S. K. Lim, Low Power Monolithic 3D IC Design of Asynchronous AES Core , Proceedings of the 21st International Symposium on Asynchronous Circuits and Systems, pp. 93-99, 2015.
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Hazards and Formal Verification
- E. B. Eichelberger, Hazard Detection in Combinational and Sequential Switching Circuits , IBM Journal of Research and Development, Volume 9, Issue 2, pp. 90-99, 1965
- S. H. Unger, Hazards, Critical Races, and Metastability , IEEE Transactions on Computers, Volume 44, Issue 6, pp. 754-768, 1995.
- F. Shi and Y. Makris, SPIN-SIM: Logic and Fault Simulation for Speed-Independent Circuits , Proceedings of the ITC 2004, pp. 597-606, 2004.
- Y. Xu and K. S. Stevens, Automatic Synthesis of Computation Interference Constraints for Relative Timing Verification , Proceedings of ICCD 2009, pp. 16-22, 2009.
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Indicating Logic (with Completion Detection)
- J. Sparso, J. Staunstrup, M. D. Sorensen, Design of delay insensitive circuits using multi-ring structures , Proceedings of EURO-DAC 1996, pp. 15-20, 1996.
- M. Linthart, K. Fant, R. Smith, A. Taubin and A. Kondratyev, Asynchronous Design Using Commercial HDL Synthesis Tools , Proceedings of ASYNC 2000, pp. 114-125, 2000.
- A. Kondratyev, K. Lwin, Design of Asynchronous Circuits by Synchronous CAD Tools , Proceedings of the 39th DAC, pp. 411-414, 2002.
- J. Cortadella, A. Kondratyev, L. Lavagno and C. Sotiriou, Coping with the Variability of Combinational Logic Delays , Proceedings of ICCD 2004, pp. 505-508, 2004.
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Place Transition (PTnets) or Petri-Nets
- T. Murata, Petri Nets: Properties, Analysis and Applications , Proceedings of the IEEE, Volume 77, Issue 4, pp. 541-580, 1989.
- J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno and A. Yakovlev, A Region-Based Theory for State Assignment in Speed-Independent Circuits , IEEE Transactions on CAD, Volume 16, Issue 8, pp. 793-812, 2002.
- R. Cordone, L. Ferrarini and L. Piroddi, Some Results on the Computation of Minimal Siphons in Petri Nets> , Proceedings of 42nd IEEE Conference on Decision and Control, Volume 4, pp. 3754-3759, 2003.
- J. Esparza, E. Best, M. Silva, Minimal Deadlocks in Free Choice Nets , Universitat Hildesheim. Institut fur Informatik, 1989.
- P. Kemper and F. Bause, An Efficient Polynomial-Time Algorithm to Decide Liveness and Boundedness of Free-Choice Nets , Application and Theory of Petri Nets 1992. Springer Berlin Heidelberg, pp. 263-278m, 1992.
- P. M. Mattheakis, C. P. Sotiriou and P. A. Beerel, A Polynomial Time Flow For Implementing Free-Choice Petri-Nets , ICCD 2012, pp. 227-234, 2012.
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Timing Analysis and Optimisation
- C. V. Ramamoorthy and G. S. Ho, Performance Evaluation of Asynchronous Concurrent Systems Using Petri Nets , IEEE Transactions on Software Engineering, Volume SE-6, Issue 5, pp. 440-449, 1980
- J. Maggott, Performance Evaluation of Concurrent Systems using Petri Nets , Information Processing Letters 18, p. 7-13, 1984.
- R. M. Karp, A Characterization of the Minimum Cycle Mean in a Digraph , Discrete Mathematics, Volume 23, Issue 3, pp. 309-311, 1978.
- H. Hulgaard, S. Burns, T. Amon and G. Borriello, An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems , IEEE Transactions on Computers, Volume 44, Issue 11, 2002.
- S. Kim and P. Beerel, Pipeline Optimization for Asynchronous Circuits: Complexity Analysis and an Efficient Optimal Algorithm , IEEE Transactions on CAD, Volume 25, Issue 3, pp. 389-402, 2006
C. P. Sotiriou - Last Updated - 11/12/2015.