CE 658: ADVANCED TOPICS IN COMPUTER ARCHITECTURE -- FALL 2018

DATE	TOPIC	SLIDES	COMMENTS
22/01/2019	Transactional Memory	Lecture12	[TC] Lance Hammond et al., "Transactional Memory Coherence and Consistency", International Symposium of Computer Architecture (ISCA), 2004 [NI] Poonacha Kongetira, et al., "Niagara: A 32-bit Multithreaded SPARC Processor," IEEE Micro Magazine, March/April 2005
08/01/2018	Memory Consistency	Lecture11	[MC] Sarita Adve et al., "Memory Consistency: A Tutorial", Rice University Technical Report, 1995
18/12/2018	Distributed Shared Memory Architectures, Directory-Based Memory Coherence, Synchronization	Lecture10
11/12/2018	Shared Memory Multiprocessors - Memory Coherence	Lecture9
04/12/2018	Simultaneous Multithreading (SMT) - Case study: IBM Power server architecture	Lecture8	[SMT] Dean M Tulsen et al, "Simultaneous Multithreading: Maximizing On-Chip Parallelism", ISCA, 1995 [P6] H.Q. Le, et al, "IBM Power 6 Microarchitecture," IBM Journal of Research and Development, November 2007
27/11/2018	Case study: CUDA and GPU architectures	Lecture7
13/11/2018 20/11/2018	Compile-time scheduling - Superblocks, Hyperblocks, Predication, Speculation Case study: Itanium ISA	Lecture6	[SB] W.m. Hwu et al, "The Superblock: An Effective Technique for VLIW and Superscalar Compilation", The Journal of Supercomputing, 1993 [HB] CT Hwuang, et. al S. Mahlke et al, “Effective Compiler Support for Predicated Execution Using the Hyperblock,” MICRO 24, December 1992 [IMP] D. August et al, “Integrated Predicated and Speculative Execution in the IMPACT EPIC architecture”, ISCA, June 1998
13/11/2018	Compile-time scheduling - Modulo Scheduling Algorithms	Lecture5	[ModSched] B. Rau, et. al “Code Generation Schema for Modulo Scheduled Loops,” Micro 24, December 1992 [PLS] CT Hwuang, et. al “PLS: A Scheduler for Pipeline Synthesis,” IEEE Transactions on CAD, September 1993 [SMS] Josep Llosa, et. al. “Swing Modulo Scheduling: A Life-Time Sensitive Approach,” PACT 1996
06/11/2018	Case study: Nehalem microarchitecture	Lecture4	Presentation of Intel's Nehalem microarachitecture at Intel's development forum
23/10/2018 30/10/2018	ILP - Dynamic scheduling	Lecture3	An animated presentation of Tomasulo's algorithm and Reorder Buffers. Source: Jim Smith and Andrew Pleszkun. Implementing Precise Interrupts in Pipelined Processors. IEEE Transactions on Computers. May 1988
16/10/2018	Administrative Introduction to Parallel Computer Architecture	Lecture1	Read the papers for homework 1

22/01/2019

Transactional Memory

[TC] Lance Hammond et al., "Transactional Memory Coherence and Consistency", International Symposium of Computer Architecture (ISCA), 2004
[NI] Poonacha Kongetira, et al., "Niagara: A 32-bit Multithreaded SPARC Processor," IEEE Micro Magazine, March/April 2005

08/01/2018

Memory Consistency

Lecture11

[MC] Sarita Adve et al., "Memory Consistency: A Tutorial", Rice University Technical Report, 1995

18/12/2018

Distributed Shared Memory Architectures,
Directory-Based Memory Coherence,
Synchronization

Lecture10

11/12/2018

Shared Memory Multiprocessors - Memory Coherence

Lecture9

04/12/2018

Simultaneous Multithreading (SMT) - Case study: IBM Power server architecture

Lecture8

[SMT] Dean M Tulsen et al, "Simultaneous Multithreading: Maximizing On-Chip Parallelism", ISCA, 1995
[P6] H.Q. Le, et al, "IBM Power 6 Microarchitecture," IBM Journal of Research and Development, November 2007

27/11/2018

Case study: CUDA and GPU architectures

Lecture7

13/11/2018
20/11/2018

Compile-time scheduling - Superblocks, Hyperblocks, Predication, Speculation
Case study: Itanium ISA

Lecture6

[SB] W.m. Hwu et al, "The Superblock: An Effective Technique for VLIW and Superscalar Compilation", The Journal of Supercomputing, 1993
[HB] CT Hwuang, et. al S. Mahlke et al, “Effective Compiler Support for Predicated Execution Using the Hyperblock,” MICRO 24, December 1992
[IMP] D. August et al, “Integrated Predicated and Speculative Execution in the IMPACT EPIC architecture”, ISCA, June 1998

13/11/2018

Compile-time scheduling - Modulo Scheduling Algorithms

Lecture5

[ModSched] B. Rau, et. al “Code Generation Schema for Modulo Scheduled Loops,” Micro 24, December 1992
[PLS] CT Hwuang, et. al “PLS: A Scheduler for Pipeline Synthesis,” IEEE Transactions on CAD, September 1993
[SMS] Josep Llosa, et. al. “Swing Modulo Scheduling: A Life-Time Sensitive Approach,” PACT 1996

06/11/2018

Case study: Nehalem microarchitecture

Lecture4

Presentation of Intel's Nehalem microarachitecture at Intel's development forum

23/10/2018
30/10/2018

ILP - Dynamic scheduling

Lecture3

An animated presentation of Tomasulo's algorithm and Reorder Buffers.
Source: Jim Smith and Andrew Pleszkun. Implementing Precise Interrupts in Pipelined Processors. IEEE Transactions on Computers. May 1988

16/10/2018

Administrative
Introduction to Parallel Computer Architecture

Lecture1

Read the papers for homework 1

Lecture Notes