ECE 435: EMBEDDED SYSTEMS
Spring 2019

Final Labs and Project

Goal

The main goal of the final labs and the project is to explore an idea that interests you that involves modifying FPGA hardware and software to increase the performance of a parallel workload.
You can do those Labs and the final project alone or in a team of two. We recommend that you form a team: not only will you be able to tackle a more interesting project, but you will also more than double the quality of the project by having someone else to brainstorm with.

Project scope

You will want to spend a bit of time identifying a project idea that is substantial enough to be interesting, yet simple enough to be tackled in just one month. The purpose of sending us a project abstract early on is to let us help you choose a good balance between ambition and tractability. We would expect a final project to have a more thorough correctness and performance evaluation than we asked for in the labs. You will want to choose not just a hardware/software idea for improving performance, but also a parallel application to use to show that your ideas improve performance. Please do talk to the instructor about your ideas.

The report

At the end of the semester, we would like to to receive a project report from you, with the following outline. You should use the ACM template to write your report.