Spring 2019


16/04/2019 SoC Design and Optimization sobel.rar
Lab5 Documentation
In this lab you will execute and profile the Sobel filter application on the ARM processor.
Then, you will develop an equivalent hardware accelerator using Vivado HLS, test its functionality and integrate it to the SoC. You will optimize both solutions and compare them in terms of performance. Lab deadline is at the end of the Exam period around 20/06.
29/03/2019 Software and Hardware Optimizations  
Lab4 Documentation
In this lab you will develop a software application on the ARM processor and you will profile the application to assess its performance footprint.
Then, you will develop an equivalent hardware accelerator, test its functionality and integrate it to the SoC. Finally, you will profile both solutions and propose solutions to improve performance in each case. Deadline is Thursday, 12/04/2019.
15/03/2019 Adding Custom IP to the SoC lab3.rar
Lab3 Documentation
This lab combines the hardware and software capabilities of Zedboard. In the first part of Lab3 you create the hardware and software components of a custom peripheral and you add the peripheral to the SoC of Lab2.
In the second part, you explore the capabilities of hardware debug. The third part combines all the work that you did on the previous labs. You will add the Gray Code hardware IP as an AXI4 peripheral and add code to control/monitor its functionality on the Zedboard. Deadline is Thursday 29/03/2019.
01/03/2019 Simple Processor-Based SoC Design and Software Development C source codes lab2.tar and CoreMark benchmark suite
Lab2 Documentation
In the second Lab you create an ARM-based hardware and software system targeting the Zedboard.
Besides working on this lab, you should take the time to study the user manuals of Zedboard, ARM processor. Deadline is Tuesday 12/3/2019.
15/02/2019 Hardware Design on the Zedboard FPGA lab1.tar
Lab1 Documentation
The first lab uses your Verilog skills to design an N-bit Gray counter, perform behavioral simulation, and download and test the counter on the Zedboard FPGA board.
Use the given Verilog sceleton files as a guide to build your modules for each one of the five steps of Lab1. Deadline is Friday, 01/03/2019.