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# Generated by: PathVIZ (Version: 1.0)
# OS: Linux x86_64(Host: sunfire)
# Generated on: Wed Apr 20 10:11:24 2016
# Design: counter
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# Core Utilisation: 48%
# Core Width, Height: 4.950, 5.184, Aspect Ratio: 0.955
# Core X, Y Offsets: 0.090, 0.576
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# Rows
Row: COREROW_0 Type: CORE Location: 0.090 0.576 Width/Height: 4.950 0.576
Row: COREROW_1 Type: CORE Location: 0.090 1.152 Width/Height: 4.950 0.576
Row: COREROW_2 Type: CORE Location: 0.090 1.728 Width/Height: 4.950 0.576
Row: COREROW_3 Type: CORE Location: 0.090 2.304 Width/Height: 4.950 0.576
Row: COREROW_4 Type: CORE Location: 0.090 2.880 Width/Height: 4.950 0.576
Row: COREROW_5 Type: CORE Location: 0.090 3.456 Width/Height: 4.950 0.576
Row: COREROW_6 Type: CORE Location: 0.090 4.032 Width/Height: 4.950 0.576
Row: COREROW_7 Type: CORE Location: 0.090 4.608 Width/Height: 4.950 0.576
Row: COREROW_8 Type: CORE Location: 0.090 5.184 Width/Height: 4.950 0.576
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# Top-Level I/O Ports 
IO: count|7 Location: 0.070 0.000
# WEST SIDE
IO: count|6 Location: 0.210 6.300
# SOUTH SIDE
IO: count|5 Location: 5.110 0.100
# EAST SIDE
IO: count|4 Location: 0.210 0.000
# NORTH SIDE
IO: count|3 Location: 0.070 0.100
# WEST SIDE
IO: count|2 Location: 0.350 6.300
# SOUTH SIDE
IO: count|1 Location: 5.110 0.200
# EAST SIDE
IO: count|0 Location: 0.350 0.000
# NORTH SIDE
IO: clk Location: 0.070 0.200
# WEST SIDE
IO: reset Location: 0.490 6.300
# SOUTH SIDE
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# Top-Level I/O CCs 
IO: count|7 CCs: counter/\count_reg[7] counter_DW01_inc_0/U2 
IO: count|6 CCs: counter/\count_reg[6] counter_DW01_inc_0/U1_1_6 
IO: count|5 CCs: counter/\count_reg[5] counter_DW01_inc_0/U1_1_5 
IO: count|4 CCs: counter/\count_reg[4] counter_DW01_inc_0/U1_1_4 
IO: count|3 CCs: counter/\count_reg[3] counter_DW01_inc_0/U1_1_3 
IO: count|2 CCs: counter/\count_reg[2] counter_DW01_inc_0/U1_1_2 
IO: count|1 CCs: counter/\count_reg[1] counter_DW01_inc_0/U1_1_1 
IO: count|0 CCs: counter/\count_reg[0] counter_DW01_inc_0/U1_1_1 counter_DW01_inc_0/U1 
IO: clk CCs: counter/\count_reg[7] counter/\count_reg[4] counter/\count_reg[5] counter/\count_reg[6] counter/\count_reg[2] counter/\count_reg[3] counter/\count_reg[1] counter/\count_reg[0] 
IO: reset CCs: counter/U4 
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# Component CCs 
Component: counter_DW01_inc_0/U1_1_4 CCs: counter/\count_reg[4] counter_DW01_inc_0/U1_1_3 counter_DW01_inc_0/U1_1_5 
Component: counter/\count_reg[2] CCs: counter/U4 counter_DW01_inc_0/U1_1_2 
Component: counter_DW01_inc_0/U1_1_5 CCs: counter/\count_reg[5] counter_DW01_inc_0/U1_1_4 counter_DW01_inc_0/U1_1_6 
Component: counter_DW01_inc_0/U2 CCs: counter_DW01_inc_0/U1_1_6 counter/\count_reg[7] 
Component: counter/\count_reg[6] CCs: counter/U4 counter_DW01_inc_0/U1_1_6 
Component: counter/\count_reg[3] CCs: counter/U4 counter_DW01_inc_0/U1_1_3 
Component: counter/U4 CCs: counter/\count_reg[7] counter/\count_reg[4] counter/\count_reg[5] counter/\count_reg[6] counter/\count_reg[2] counter/\count_reg[3] counter/\count_reg[1] counter/\count_reg[0] 
Component: counter/\count_reg[0] CCs: counter/U4 counter_DW01_inc_0/U1 counter_DW01_inc_0/U1_1_1 
Component: counter_DW01_inc_0/U1 CCs: counter/\count_reg[0] 
Component: counter/\count_reg[7] CCs: counter/U4 counter_DW01_inc_0/U2 
Component: counter/\count_reg[4] CCs: counter/U4 counter_DW01_inc_0/U1_1_4 
Component: counter/\count_reg[1] CCs: counter/U4 counter_DW01_inc_0/U1_1_1 
Component: counter_DW01_inc_0/U1_1_2 CCs: counter/\count_reg[2] counter_DW01_inc_0/U1_1_1 counter_DW01_inc_0/U1_1_3 
Component: counter_DW01_inc_0/U1_1_3 CCs: counter/\count_reg[3] counter_DW01_inc_0/U1_1_2 counter_DW01_inc_0/U1_1_4 
Component: counter/\count_reg[5] CCs: counter/U4 counter_DW01_inc_0/U1_1_5 
Component: counter_DW01_inc_0/U1_1_1 CCs: counter/\count_reg[1] counter/\count_reg[0] counter_DW01_inc_0/U1_1_2 
Component: counter_DW01_inc_0/U1_1_6 CCs: counter/\count_reg[6] counter_DW01_inc_0/U1_1_5 counter_DW01_inc_0/U2