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# Generated by: PathVIZ (Version: 1.0)
# OS: Linux x86_64(Host: sunfire)
# Generated on: Wed Apr 20 10:37:28 2016
# Design: ALU
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# Core Utilisation: 50%
# Core Width, Height: 9.270, 9.216, Aspect Ratio: 1.006
# Core X, Y Offsets: 0.090, 0.576
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# Rows
Row: COREROW_0 Type: CORE Location: 0.090 0.576 Width/Height: 9.270 0.576
Row: COREROW_1 Type: CORE Location: 0.090 1.152 Width/Height: 9.270 0.576
Row: COREROW_2 Type: CORE Location: 0.090 1.728 Width/Height: 9.270 0.576
Row: COREROW_3 Type: CORE Location: 0.090 2.304 Width/Height: 9.270 0.576
Row: COREROW_4 Type: CORE Location: 0.090 2.880 Width/Height: 9.270 0.576
Row: COREROW_5 Type: CORE Location: 0.090 3.456 Width/Height: 9.270 0.576
Row: COREROW_6 Type: CORE Location: 0.090 4.032 Width/Height: 9.270 0.576
Row: COREROW_7 Type: CORE Location: 0.090 4.608 Width/Height: 9.270 0.576
Row: COREROW_8 Type: CORE Location: 0.090 5.184 Width/Height: 9.270 0.576
Row: COREROW_9 Type: CORE Location: 0.090 5.760 Width/Height: 9.270 0.576
Row: COREROW_10 Type: CORE Location: 0.090 6.336 Width/Height: 9.270 0.576
Row: COREROW_11 Type: CORE Location: 0.090 6.912 Width/Height: 9.270 0.576
Row: COREROW_12 Type: CORE Location: 0.090 7.488 Width/Height: 9.270 0.576
Row: COREROW_13 Type: CORE Location: 0.090 8.064 Width/Height: 9.270 0.576
Row: COREROW_14 Type: CORE Location: 0.090 8.640 Width/Height: 9.270 0.576
Row: COREROW_15 Type: CORE Location: 0.090 9.216 Width/Height: 9.270 0.576
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# Top-Level I/O Ports 
IO: alucount|7 Location: 0.070 0.000
# WEST SIDE
IO: alucount|6 Location: 0.070 10.300
# SOUTH SIDE
IO: alucount|5 Location: 9.310 0.000
# EAST SIDE
IO: alucount|4 Location: 0.210 0.000
# NORTH SIDE
IO: alucount|3 Location: 0.070 0.100
# WEST SIDE
IO: alucount|2 Location: 0.210 10.300
# SOUTH SIDE
IO: alucount|1 Location: 9.310 0.100
# EAST SIDE
IO: alucount|0 Location: 0.350 0.000
# NORTH SIDE
IO: alucount2|7 Location: 0.070 0.200
# WEST SIDE
IO: alucount2|6 Location: 0.350 10.300
# SOUTH SIDE
IO: alucount2|5 Location: 9.310 0.200
# EAST SIDE
IO: alucount2|4 Location: 0.490 0.000
# NORTH SIDE
IO: alucount2|3 Location: 0.070 0.300
# WEST SIDE
IO: alucount2|2 Location: 0.490 10.300
# SOUTH SIDE
IO: alucount2|1 Location: 9.310 0.300
# EAST SIDE
IO: alucount2|0 Location: 0.630 0.000
# NORTH SIDE
IO: alucount3|7 Location: 0.070 0.400
# WEST SIDE
IO: alucount3|6 Location: 0.630 10.300
# SOUTH SIDE
IO: alucount3|5 Location: 9.310 0.400
# EAST SIDE
IO: alucount3|4 Location: 0.770 0.000
# NORTH SIDE
IO: alucount3|3 Location: 0.070 0.500
# WEST SIDE
IO: alucount3|2 Location: 0.770 10.300
# SOUTH SIDE
IO: alucount3|1 Location: 9.310 0.500
# EAST SIDE
IO: alucount3|0 Location: 0.910 0.000
# NORTH SIDE
IO: clk Location: 0.070 0.600
# WEST SIDE
IO: reset Location: 0.910 10.300
# SOUTH SIDE
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# Top-Level I/O CCs 
IO: alucount|7 CCs: counter_DW01_inc_0/U2 counter/\count_reg[7] 
IO: alucount|6 CCs: counter_DW01_inc_0/U1_1_6 counter/\count_reg[6] 
IO: alucount|5 CCs: counter_DW01_inc_0/U1_1_5 counter/\count_reg[5] 
IO: alucount|4 CCs: counter_DW01_inc_0/U1_1_4 counter/\count_reg[4] 
IO: alucount|3 CCs: counter_DW01_inc_0/U1_1_3 counter/\count_reg[3] 
IO: alucount|2 CCs: counter_DW01_inc_0/U1_1_2 counter/\count_reg[2] 
IO: alucount|1 CCs: counter_DW01_inc_0/U1_1_1 counter/\count_reg[1] 
IO: alucount|0 CCs: counter_DW01_inc_0/U1_1_1 counter_DW01_inc_0/U1 counter/\count_reg[0] 
IO: alucount2|7 CCs: counter_DW01_inc_1/U2 counter2/\count_reg[7] 
IO: alucount2|6 CCs: counter_DW01_inc_1/U1_1_6 counter2/\count_reg[6] 
IO: alucount2|5 CCs: counter_DW01_inc_1/U1_1_5 counter2/\count_reg[5] 
IO: alucount2|4 CCs: counter_DW01_inc_1/U1_1_4 counter2/\count_reg[4] 
IO: alucount2|3 CCs: counter_DW01_inc_1/U1_1_3 counter2/\count_reg[3] 
IO: alucount2|2 CCs: counter_DW01_inc_1/U1_1_2 counter2/\count_reg[2] 
IO: alucount2|1 CCs: counter_DW01_inc_1/U1_1_1 counter2/\count_reg[1] 
IO: alucount2|0 CCs: counter_DW01_inc_1/U1_1_1 counter_DW01_inc_1/U1 counter2/\count_reg[0] 
IO: alucount3|7 CCs: counter_DW01_inc_2/U2 counter3/\count_reg[7] 
IO: alucount3|6 CCs: counter_DW01_inc_2/U1_1_6 counter3/\count_reg[6] 
IO: alucount3|5 CCs: counter_DW01_inc_2/U1_1_5 counter3/\count_reg[5] 
IO: alucount3|4 CCs: counter_DW01_inc_2/U1_1_4 counter3/\count_reg[4] 
IO: alucount3|3 CCs: counter_DW01_inc_2/U1_1_3 counter3/\count_reg[3] 
IO: alucount3|2 CCs: counter_DW01_inc_2/U1_1_2 counter3/\count_reg[2] 
IO: alucount3|1 CCs: counter_DW01_inc_2/U1_1_1 counter3/\count_reg[1] 
IO: alucount3|0 CCs: counter_DW01_inc_2/U1_1_1 counter_DW01_inc_2/U1 counter3/\count_reg[0] 
IO: clk CCs: counter3/\count_reg[7] counter3/\count_reg[4] counter3/\count_reg[5] counter3/\count_reg[6] counter3/\count_reg[2] counter3/\count_reg[3] counter3/\count_reg[1] counter3/\count_reg[0] counter2/\count_reg[7] counter2/\count_reg[4] counter2/\count_reg[5] counter2/\count_reg[6] counter2/\count_reg[2] counter2/\count_reg[3] counter2/\count_reg[1] counter2/\count_reg[0] counter/\count_reg[7] counter/\count_reg[4] counter/\count_reg[5] counter/\count_reg[6] counter/\count_reg[2] counter/\count_reg[3] counter/\count_reg[1] counter/\count_reg[0] 
IO: reset CCs: ALU/alu_u1 
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# Component CCs 
Component: counter/\count_reg[1] CCs: counter/U4 counter_DW01_inc_0/U1_1_1 
Component: counter2/U6 CCs: counter2/U5 counter2/\count_reg[7] counter2/\count_reg[4] counter2/\count_reg[5] counter2/\count_reg[6] counter2/\count_reg[2] counter2/\count_reg[3] counter2/\count_reg[1] counter2/\count_reg[0] 
Component: counter/\count_reg[3] CCs: counter/U4 counter_DW01_inc_0/U1_1_3 
Component: counter_DW01_inc_2/U1 CCs: counter3/\count_reg[0] 
Component: counter_DW01_inc_2/U2 CCs: counter_DW01_inc_2/U1_1_6 counter3/\count_reg[7] 
Component: counter/\count_reg[5] CCs: counter/U4 counter_DW01_inc_0/U1_1_5 
Component: counter/\count_reg[7] CCs: counter/U4 counter_DW01_inc_0/U2 
Component: counter2/\count_reg[1] CCs: counter2/U6 counter_DW01_inc_1/U1_1_1 
Component: counter2/\count_reg[3] CCs: counter2/U6 counter_DW01_inc_1/U1_1_3 
Component: counter_DW01_inc_2/U1_1_1 CCs: counter3/\count_reg[1] counter3/\count_reg[0] counter_DW01_inc_2/U1_1_2 
Component: counter_DW01_inc_2/U1_1_2 CCs: counter3/\count_reg[2] counter_DW01_inc_2/U1_1_1 counter_DW01_inc_2/U1_1_3 
Component: counter_DW01_inc_2/U1_1_3 CCs: counter3/\count_reg[3] counter_DW01_inc_2/U1_1_2 counter_DW01_inc_2/U1_1_4 
Component: counter_DW01_inc_0/U2 CCs: counter_DW01_inc_0/U1_1_6 counter/\count_reg[7] 
Component: counter_DW01_inc_2/U1_1_4 CCs: counter3/\count_reg[4] counter_DW01_inc_2/U1_1_3 counter_DW01_inc_2/U1_1_5 
Component: counter_DW01_inc_2/U1_1_5 CCs: counter3/\count_reg[5] counter_DW01_inc_2/U1_1_4 counter_DW01_inc_2/U1_1_6 
Component: counter2/\count_reg[5] CCs: counter2/U6 counter_DW01_inc_1/U1_1_5 
Component: counter_DW01_inc_2/U1_1_6 CCs: counter3/\count_reg[6] counter_DW01_inc_2/U1_1_5 counter_DW01_inc_2/U2 
Component: counter2/\count_reg[7] CCs: counter2/U6 counter_DW01_inc_1/U2 
Component: counter3/\count_reg[2] CCs: counter3/U8 counter_DW01_inc_2/U1_1_2 
Component: counter_DW01_inc_0/U1 CCs: counter/\count_reg[0] 
Component: counter3/\count_reg[0] CCs: counter3/U8 counter_DW01_inc_2/U1 counter_DW01_inc_2/U1_1_1 
Component: counter3/\count_reg[6] CCs: counter3/U8 counter_DW01_inc_2/U1_1_6 
Component: counter3/\count_reg[4] CCs: counter3/U8 counter_DW01_inc_2/U1_1_4 
Component: counter/\count_reg[2] CCs: counter/U4 counter_DW01_inc_0/U1_1_2 
Component: counter/\count_reg[0] CCs: counter/U4 counter_DW01_inc_0/U1 counter_DW01_inc_0/U1_1_1 
Component: ALU/alu_u1 CCs: ALU/alu_u2 
Component: ALU/alu_u2 CCs: ALU/alu_u1 counter3/U4 counter2/U4 counter/U4 
Component: counter/\count_reg[6] CCs: counter/U4 counter_DW01_inc_0/U1_1_6 
Component: counter/\count_reg[4] CCs: counter/U4 counter_DW01_inc_0/U1_1_4 
Component: counter3/U8 CCs: counter3/U7 counter3/\count_reg[7] counter3/\count_reg[4] counter3/\count_reg[5] counter3/\count_reg[6] counter3/\count_reg[2] counter3/\count_reg[3] counter3/\count_reg[1] counter3/\count_reg[0] 
Component: counter_DW01_inc_0/U1_1_2 CCs: counter/\count_reg[2] counter_DW01_inc_0/U1_1_1 counter_DW01_inc_0/U1_1_3 
Component: counter2/\count_reg[2] CCs: counter2/U6 counter_DW01_inc_1/U1_1_2 
Component: counter_DW01_inc_0/U1_1_3 CCs: counter/\count_reg[3] counter_DW01_inc_0/U1_1_2 counter_DW01_inc_0/U1_1_4 
Component: counter/U4 CCs: ALU/alu_u2 counter/\count_reg[7] counter/\count_reg[4] counter/\count_reg[5] counter/\count_reg[6] counter/\count_reg[2] counter/\count_reg[3] counter/\count_reg[1] counter/\count_reg[0] 
Component: counter_DW01_inc_0/U1_1_1 CCs: counter/\count_reg[1] counter/\count_reg[0] counter_DW01_inc_0/U1_1_2 
Component: counter2/\count_reg[0] CCs: counter2/U6 counter_DW01_inc_1/U1 counter_DW01_inc_1/U1_1_1 
Component: counter_DW01_inc_0/U1_1_6 CCs: counter/\count_reg[6] counter_DW01_inc_0/U1_1_5 counter_DW01_inc_0/U2 
Component: counter_DW01_inc_0/U1_1_4 CCs: counter/\count_reg[4] counter_DW01_inc_0/U1_1_3 counter_DW01_inc_0/U1_1_5 
Component: counter_DW01_inc_1/U1_1_3 CCs: counter2/\count_reg[3] counter_DW01_inc_1/U1_1_2 counter_DW01_inc_1/U1_1_4 
Component: counter2/\count_reg[6] CCs: counter2/U6 counter_DW01_inc_1/U1_1_6 
Component: counter_DW01_inc_0/U1_1_5 CCs: counter/\count_reg[5] counter_DW01_inc_0/U1_1_4 counter_DW01_inc_0/U1_1_6 
Component: counter_DW01_inc_1/U1_1_2 CCs: counter2/\count_reg[2] counter_DW01_inc_1/U1_1_1 counter_DW01_inc_1/U1_1_3 
Component: counter_DW01_inc_1/U1_1_1 CCs: counter2/\count_reg[1] counter2/\count_reg[0] counter_DW01_inc_1/U1_1_2 
Component: counter3/\count_reg[3] CCs: counter3/U8 counter_DW01_inc_2/U1_1_3 
Component: counter2/\count_reg[4] CCs: counter2/U6 counter_DW01_inc_1/U1_1_4 
Component: counter3/U4 CCs: ALU/alu_u2 counter3/U5 
Component: counter3/U5 CCs: counter3/U4 counter3/U6 
Component: counter_DW01_inc_1/U1_1_6 CCs: counter2/\count_reg[6] counter_DW01_inc_1/U1_1_5 counter_DW01_inc_1/U2 
Component: counter3/\count_reg[1] CCs: counter3/U8 counter_DW01_inc_2/U1_1_1 
Component: counter3/U6 CCs: counter3/U5 counter3/U7 
Component: counter_DW01_inc_1/U1_1_5 CCs: counter2/\count_reg[5] counter_DW01_inc_1/U1_1_4 counter_DW01_inc_1/U1_1_6 
Component: counter3/U7 CCs: counter3/U6 counter3/U8 
Component: counter_DW01_inc_1/U1_1_4 CCs: counter2/\count_reg[4] counter_DW01_inc_1/U1_1_3 counter_DW01_inc_1/U1_1_5 
Component: counter3/\count_reg[7] CCs: counter3/U8 counter_DW01_inc_2/U2 
Component: counter_DW01_inc_1/U2 CCs: counter_DW01_inc_1/U1_1_6 counter2/\count_reg[7] 
Component: counter_DW01_inc_1/U1 CCs: counter2/\count_reg[0] 
Component: counter3/\count_reg[5] CCs: counter3/U8 counter_DW01_inc_2/U1_1_5 
Component: counter2/U5 CCs: counter2/U4 counter2/U6 
Component: counter2/U4 CCs: ALU/alu_u2 counter2/U5