Course Details

  1. Description

    2. The aim of CE664/CE438 is to introduce the fundamental concepts of clockless or asynchronous circuit design, relevant design styles for asynchronous control and datapath logic, high-level models for concurrent systems, as well as EDA algorithms for asynchronous logic, including logic synthesis, timing analysis, hazard detection and timing model verification.

    The course will present (1) asynchronous channel based design, using various handshake protocols, (2) template based design, including micropipelines and the De-synchronisation methodology, (3) modelling and logic synthesis of asynchronous control circuits based on PTnets and Multiple Synchronised FSMs (MSFSMs), (4) asynchronous timing models, hazards, races and their verification using multi-value logic, (5) indicating logic for datapath, (6) timing analysis and optimisation techniques for asynchronous circuits and (7) GALS systems.

  2. Syllabus

    3. The course syllabus is (roughly) as follows.

    1. Channel-Based Design, Handshaking protocols
    2. Event-driven Gates and Circuits - the C and XOR gates
    3. Micropipelines - a simple template for asynchronous pipelining
    4. Micropipeline analysis and verification - full and half buffers and deadlocks
    5. Asynchronous circuit specification using PTnets and STGs - State graph and Verification properties
    6. Fundamentals of Petri nets (or Place Transition nets - PTnets) and their application to asynchronous control circuits
    7. Asynchronous Pipeline Basics - Token Occupancy and Performance, Slack Elasticity, Latency Insensitivity, Elastic Buffering
    8. Asynchronous Timing Models - DI, QDI, Semi-Modularity, SI, Fundamental Mode, Timed
    9. Hazards and Races in Asychronous Circuits and Techniques for their detection
    10. Asynchronous template based design
    11. De-synchronisation : an automated approach for synchronous to asynchronous conversion
    12. Logic Synthesis from a PTnet specification - the Petrify approach
    13. Gate-level Model Checking of Timing Models
    14. Other Approaches - One-Hot FSMs/David Cells
    15. Indicating Logic Datapath Design and algorithms for conversion - Dual-Rail Encoding
    16. Strongly and Weakly indicating approaches, Dual-Rail Timing Assumptions gates and wire orphans
    17. DIMS, NCL, NCLX, Inverting gates DR logic
    18. the GALS approach
    19. Relative Timing and its impact on Simplifying control circuits
    20. New approaches for PTnet implementation

  3. Coursework

    4. The course will include both written-up assignments as well as small-scale programming exercises.

  4. Grading

    5. To be announced shortly...
C. P. Sotiriou - Last Updated - 9/10/2015.