17/3/2014
91
ASPIDA PCB Design
*32-bit RISC CPU with DFV and adaptive (P, V, T) timing
*DFV embedded automatically to RISC CPU Verilog netlist using NanoSync V0 tool
*700K Transistor Design,
0.25um CMOS process
*Full-scan testable, Adaptive Timing operation
*DFV Voltage Scaling from 3.3V down to 0.95V (2.5V process nominal)
*DFV Speed Scaling period from 18ns cycle @ 2.5V to 4,000ns @ 0.95V
PCB with RISC IC (back)
PCB with RISC IC (front)
Back
CE-653 - De-Synchronisation Methodology