17/3/2014
86
ASPIDA FPGA Implementation
*Xilinx Spartan IIE FPGA on a Diligent 2DE board
*FPGA contained:
–De-synchronized DLX,
–Processor memories
–VGA driver
*Implemented Xilinx ISE
*Technology-portable Verilog design
*The full integer ISA and interrupt support is included
*DLX runs the “Game of Life” Algorithm
–Fully-asynchronous
*VGA is fully synchronous
*
demo_tn1 demo_tn2
http://www.ics.forth.gr/carv/async/demo/
CE-653 - De-Synchronisation Methodology