1	CE653 – Asynchronous Circuit Design Instructor: C. Sotiriou
2	De-synchronization Theory and Fundamentals
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4	Prior work Micropipelines (Sutherland, 1989) Local generation of clocks Varshavsky et al., 1995 Kol and Ginosar, 1996 Theseus Logic (Ligthart et al., 2000) Commercial HDL synthesis tools Direct translation and special registers Phased logic (Linder and Harden, 1996) (Reese, Thornton, Traver, 2003) Conceptually similar Different handshake protocol (2 phase vs. 4 phase)
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7	Synchronous flow
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18	De-synchronized flow
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31	Flow equivalence [Guernic, Talpin, Lann, 2003]
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33	Flow equivalence = Cycle Accuracy!
34	Flow equivalence = Cycle Accuracy!
35	Synchronous Circuit
36	Synchronous Circuit
37	De-Synchronized Circuit
38	De-Synchronized Circuit
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53	Can we increase concurrency ?
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75	Live-ness? Preservation of flow-equivalence: all the generated traces are equivalent Are all traces generated ? (Is the marked graph live ?) Not always !
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78	Results regarding Live-ness At least three latches in a ring are required with only one data token circulating [Muller 1962] Theorem: any hybrid combination of protocols is live if the simple 4-phase protocol is not used Proof: any cycle has at least one token
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81	ASPIDA DLX block diagram
82	De-synchronization on FPGA
83	ASPIDA FPGA Implementation Xilinx Spartan IIE FPGA on a Diligent 2DE board FPGA contained: De-synchronized DLX, Processor memories VGA driver Implemented Xilinx ISE Technology-portable Verilog design The full integer ISA and interrupt support is included DLX runs the “Game of Life” Algorithm Fully-asynchronous VGA is fully synchronous
84	De-synchronized DLX on FPGA
85	ASPIDA ASIC Design
86	ASPIDA IC 32-bit RISC CPU EU funded research project Two fully-functional ICs were manufactured with IHP 0.25um technology Runs in both synchronous and de-synchronized modes, Direct comparison of results Measurements Performance, Voltage scaling and EME measurements On-tester functional tests Lab analysis
87	ASPIDA IC Testing
88	ASPIDA PCB Design 32-bit RISC CPU with DFV and adaptive (P, V, T) timing DFV embedded automatically to RISC CPU Verilog netlist using NanoSync V0 tool 700K Transistor Design, 0.25um CMOS process Full-scan testable, Adaptive Timing operation DFV Voltage Scaling from 3.3V down to 0.95V (2.5V process nominal) DFV Speed Scaling period from 18ns cycle @ 2.5V to 4,000ns @ 0.95V
89	ASPIDA TEM Cell Measurements
90	ASPIDA Results
91	ASPIDA Measurements Performance results Synchronous: 52 MHz De-Synchronized: all chips worked above 63 MHz ~20% Lower-power through Voltage Scaling! Power results Scaling: 200 mW (50 MHz) dropped to 98 mW (30 MHz) Chips could scale down to 0.95 V (250 KHz), well beyond allowed voltage EME reduction 30 dB (average) 50 dB (max) EME measurements were done using a TEM cell to guarantee accuracy
92	ASPIDA Schmoo Plot Period vs. VDD for desynchronized operation Fully functional on any voltage above 0.95 V
93	ASPIDA EME Results ASPIDA running Factorial on TEM
94	ASPIDA EME Results ASPIDA running Matrix on TEM
95	Energy Spreading Effect
96	Conclusions Asynchronous is NOT a Religion! Stop evangelizing goodness Axioms It is NOT about asynchronous OR synchronous! It is about clocking selectively! Need Pragmatic Design Approaches and Flows Need New EDA Tools Need New EDA Algorithms Don’t need new Library Cells for ASIC/SoC Don’t need new Silicon Architecture for FPGAs Killer Apps are here to stay; Understand them! SoC synchronization Low-Power Variability