Asynchronous
Circuits - Classes
18/3/2014
CE-653 - Hazards and Analysis
Methods
7
}Timing Model (or Class)
is used to define specific timing assumptions with respect
to correct circuit operation
}DI
}Arbitrary gate and wire
delays (unbounded)
}QDI
}DI except for Isochronic
Forks
¨No need to acknowledge
fanouts
}SI (or Muller)
circuits
}Arbitrary gate delays,
bounded wire delays
}Closed system
implementation (gate + environment)
}Fundamental Mode
(Huffman) circuits
}“Fundamental Mode”
Operation:
}Outputs and State
(local) stabilise before new input change