Sequential
Hazard Analysis
CE-653 - Hazards and Analysis
Methods
21
}Theorem 2:
}If Yk = 1(0)
after applying Procedures A and B to a sequential circuit for a given input
change starting from a given internal state, then the Yk signal
must stabilise at 1(0) for this transition, regardless of
the values of the finite delays of the logic gates
}Proof:
}Based on previous Theorem
(Theorem 1)
18/3/2014