1	CE653 – Asynchronous Circuit Design Instructor: C. Sotiriou
2	Contents Micropipeline Pitfalls Deadlocks in rings Token Occupancy in Pipeline Half-Buffer Full-Buffer C Element Extensions and Generalisations Taxonomy of Latch Controllers and Examples Micropipeline/Simple 4-phase studied earlier Analysis completed in this slide set Semi-Decoupled Fully-Decoupled De-synchronisation IPCMOS/GaSP? S-Covering vs. PTnet based Implementation
3	Micropipeline Pitfalls
4	Micropipeline Rings So far focused on Linear Pipelines A Latch Controller Ring is a very useful structure Data tokens go around the ring Represents basic iterative computation May include entry/exit points How do I build a ring? Connect Rout/Aout of RHS controller to Rin/Ain of a LHS controller Does it always work with micropipelines?
5	Micropipeline 2-Stage Ring PTnet Cycles with no tokens è Deadlock!!! Commoner’s Theorem: Deadlocked systems include an unmarked cycle Can I find a valid marking to make it live?
6	Micropipeline Analysis - MSFSMs Two-stage Micropipeline FSMs: Ring è Rin = Rout, Ain = Aout Never LIVE!!!
7	Micropipeline 3-Stage Ring Deadlocked at initial (original) marking
8	Micropipeline Analysis - MSFSMs Three-stage Micropipeline Ring FSMs: Now: Rin = Rout, Ain = Aout Live when? Rout’, Ry’, Rx initial states
9	Live Micropipeline 3-Stage Ring with Alternate Marking Live Marking Shown: Rin+, Rx+, Ry-
10	Token Occupancy – Half vs. Full Buffers
11	Full-Buffer PTnet Model
12	Half-Buffer PTnet Model
13	C Element Extensions and Generalisations
14	Boolean Function with Feedback Define: SET, KEEP and RESET functions which are feedback free RESET = U – SET (OFF-set of SET), or RESET ∩ SET = Ø KEEP = RESET’ Sole feedback of f is on the f line (feeds back to input) Form 1 (Set and Keep): f = (SET function) + f (KEEP function) Form 2 (Set and Reset): f = (SET function) + f (RESET function)’ Example Asymmetric C Element: f = bc (SET) + f (ab’)’ (RESET)’
15	Composing C Elements Based on the C-Element Boolean Equation: 2-input C-Element’s Logic Function is: c = ab + c(a + b) = ab + bc + ac n-input C-Element is: c = a₁a₂…a_n + c(a₁ + a₂ + … + a_n) It can be shown that C gates are composable using their set, keep functions: c3_{_set} = a1a2a3, c3_{_keep} = a1 + a2 + a3 c2_{_set} = a1a2, c2_{_keep} = a1 + a2 o_{_set} = a1a2, o2_{_keep} = a1 + a2 output_{_set} = (o_{_set} . a3), output_{_keep} = (o_{_keep} + a3) Thus: o_{_set} = c3_{_set}, output_{_keep} = c3_{_keep}
16	Asymmetric C Elements In certain cases, the Set and Reset logic of a C element is not identical Obvious from PTnet specification of a controller Asymmetric C elements are an extension of the basic C Equivalent to SR Latch or Boolean feedback circuit as well
17	Taxonomy of Latch Controllers
18	Taxonomy of Latch Controllers - Signals
19	Taxonomy of Latch Controllers - Timing
20	Semi-Decoupled Latch Controller
21	Semi-Decoupled Latch Controller – STG and SG A is redundant – ignore pre-buffered Lt Lt is for active-low latch,
22	Semi-Decoupled Latch Controller PTnet Latch Control L L-, L+ in PTnet
23	Semi-Decoupled Latch Controller Circuit C-gate Set, Reset functions may be inferred from STG/PTnet specification of the controller
24	Semi-Decoupled – PTnet for 3 Stages Notice how critical cycle contains two “P”s (i.e., processing steps involving delay lines)
25	Fully-Decoupled Latch Controller
26	Fully-Decoupled Latch Controller – STG and SG A again is redundant Lt is for active-low latch, B is internal signal Needed for implementation
27	Fully-Decoupled Latch Controller PTnet Latch Control L L-, L+ in PTnet Signal INT, Transitions INT+/INT- Internal For implementation purposes only
28	Fully-Decoupled Latch Controller Circuit Note Tradeoff between Concurrency and Circuit Complexity PTnet concurrency is not confluent with circuit
29	2 C-Element De-synchronisation Controller
30	2 C-Element De-Synchronisation Controller Master Latch Enable: M = (Ain != Rout) [XOR gate] Slave Latch Enable: S = (Rout == Aout) [XNOR gate]
31	2 C-Element De-Synchronisation Controller – Handshake Signals PTnet C elements obvious from PTnet Signal dependencies
32	2 C-Element De-Synchronisation Controller Need multiple instantiations of M, S signals Per control signal transition
33	2 C-Element De-Synchronisation Controller – How to Merge M, S Signals using Choice Note: PTnet is now AC
34	2 C-Element De-Synchronisation Controller Analysis - PTnets Reduction to Latch Control Signals (Verify) Characteristic Pattern:
35	De-Synchronisation Maximum Concurrency Controller
36	De-Synchronisation Maximum Concurrency Controller