}consists of 3 set-reset latches
}RHS latch produces Q, Q’
}Verbal
functional explanation quite complex and non-intuitive
}when input D is high, lower LHS latch is set whenever the
clock is low
}thus, the set input of the
upper LHS latch is triggered, which sets the output latch (RHS)
whenever the clock is high
}when input is D low, lower LHS latch is reset, thus
resetting the output latch (RHS), whenever the clock is high
}As
a result, Q may only change state when clock makes a lowàhigh transition