Mixed SRDR Circuits
20/4/2014
CE-653 - Indicating Logic
72
}DR circuits benefits and drawbacks
}Data-dependent latency (+)
}Large area overhead (-)
}Large power overhead (-)
}NULL (RESET) phase is slow!!! (-)
}Why not implemented Mixed SR and DR Logic?
}Slice C.L. circuit’s Logic Levels vertically
}Use conventional Boolean (SR) logic for first logic levels of C.L.
}Traversed anyway by most exercised circuit paths
}Use DR logic only for deep logic levels
}Exhibit data-dependent elasticity
}Hide NULL phase of DR Logic
}Overlap with SR evaluation!!!
}
}
}