Timing Assumptions
Example – SI Netlist – Adding Timing
Assumptions – Boolean Logic
CE-653 - STG-based Logic
Synthesis - Petrify
63
}Original Circuit had CSC
issue!!!
DTACK
DSr
D
LDTACK
00
01
11
10
00
01
11
10
DTACK
DSr
D
LDTACK
00
01
11
10
00
01
11
10
LDS = 0
LDS = 1
0
1
-
0
0
0
0
0
0
0/1?
1
1
1
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
