Understanding SI Model
CE-653 - STG-based Logic Synthesis - Petrify
4
}Check circuit for disabled transitions in State Graph:
}
}
}
}
}
}Disabled transitions 1*à1 or 0*à0 in the State Graph
}Thus circuit is not SI
}Circuit is also not semi-modular
}
}This analysis assumes the unbounded delay model
a
b
c
0*0*0
State Graph <a, b, c>
10*0*
0*10*
110*
1*1*1*
1*01
01*1
001*
OR