Understanding SI Model
CE-653 - STG-based Logic Synthesis - Petrify
3
}Check circuit for disabled transitions in State Graph:
}
}
}
}
}
}There are no disabled transitions
1*à1 or 0*à0 in the State Graph
}Thus circuit is SI
}
}This analysis assumes the unbounded delay model
C
a
b
c
0*0*0
State Graph <a, b, c>
10*0
0*10
110*
1*1*1
1*01
01*1
001*