Timing
Assumptions
CE-653 - STG-based Logic
Synthesis - Petrify
56
}Relative Timing
Assumptions can significantly reduce
circuit complexity
circuit complexity
}Timing assumptions
effectively remove or make redundant PTnet/STG edges
}Extreme example:
}Ain is not necessary, as controller and receiver are faster than sender
}Each timing assumption
must be guaranteed by
timing constraints at schematic or physical level or even system level
timing constraints at schematic or physical level or even system level
}Relative Timing
Assumptions can be used to optimise timing by a great deal!