Logic
Decomposition - Example
CE-653 - STG-based Logic
Synthesis - Petrify
55
}Signal s can now be added back to
the STG/PTnet
s-
s+
s-
s-
s=1
s=0
1001
1011
1000
1010
0111
0011
y+
x-
w+
z+
z-
0001
0000
0101
0010
0100
0110
x+
w-
w-
w-
z-
z-
y+
y+
x+
x+
1001
1000
1010
y+
z-
0111
y-
y-
z-
w-
y+
x+
z+
x-
s-
s+
