STG Based Logic Synthesis - the Petrify Approach

Synthesis Exercise – z Output

CE-653 - STG-based Logic Synthesis - Petrify

51

wx

yz

00

01

11

10

00

01

11

10

-

-

-

-

Signal z

1

0

0

0

0

1

1

1

0

0

0

0

1011

0111

0011

1001

1000

1010

0001

0000

0101

0010

0100

0110

y-

y+

x-

x+

w+

w-

z+

z-

w-

w-

z-

z-

y+

y+

x+

x+