Synthesis
Exercise
CE-653 - STG-based Logic
Synthesis - Petrify
49
}Derive circuits for outputs x and z
}Both complex gate and C-element based implementations
y-
z-
w-
y+
x+
z+
x-
w+
1001
1000
1010
0001
0000
0101
0010
0100
0110
y-
y+
x-
x+
w+
w-
z+
z-
w-
w-
z-
z-
y+
y+
x+
x+