STG Based Logic Synthesis - the Petrify Approach

C-Element Based Example

CE-653 - STG-based Logic Synthesis - Petrify

0000

1000

1100

0100

0110

0111

1111

1011

0011

1001

0001

}If the Reset R = a’c’ has an unbounded delay

}Then, starting from state 0000:

}a+ ; R- ; b+ ; a- ; c+ ; S+ ; d+ ;

}

}The a-, c+ transition can cause a hazard at the Reset logic

}