SI Asynchronous Circuit Synthesis
CE-653 - STG-based Logic Synthesis - Petrify
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}Goal:
}Derive a hazard-free circuit under a given delay model and mode of operation
}Speed Independence
}Unbounded gate / environment delays
}Certain wire delays shorter than certain paths in the circuit
}Wires LONGER than GATES!!!
}SI Implementability Conditions
}Consistency
}Signal transitions alternate in all PTnet paths and thus Reachability Graph
}Complete State Coding (CSC)
}Each pair of Reachability Graph States have different state encoding, or if the share the same encoding, they enable different non-input (output) signals è distinguishable
}Persistency è Semi-Modularity
}Outputs cannot be disabled once enabled, Inputs cannot be disabled by Outputs
}
}