Delay Line Design
}
}Symmetric
}Designed with an even # of inverters that model worst-case path delay through combinational logic
}
}
}
}Asymmetric
}Faster reset implemented by replacing some INVs with NANDs
}
}
}
}Other
}May also use re-create path of gates along critical path to better match delay
17/3/2014
25
CE-653 - Micropipeline Templates