Bundled-Data
Concept
}Static combinational logic (typically) and standard FFs or
latches
}Channels use bundled-data protocol
}Delay line matches worst-case delay of combinational logic
}Margin limits performance, particularly because adds to forward
latency
}Controller CTRL drives local clock to bank of FFs (or
latches)
}Designed using known
templates or burst-mode controllers, signal-transition graphs, or syntax directed
translation
17/3/2014
12
CE-653 - Micropipeline
Templates