1	CE653 – Asynchronous Circuit Design Instructor: C. Sotiriou
2	Contents Event-driven Gates: C and XOR The C Element and potential implementations C element formal models The Micropipeline event structure Micropipeline analysis using PTnets and FSMs Bundled-data concept Four-Phase Micropipeline structure Two-phase signalling Two-phase Micropipeline with simple or delayed CP signals Other Controller types: Semi and Fully-decoupled Latch Controller Delay Line Design
3	The C Element AND gate for events What is the OR gate equivalent for events?
4	C-Element Implementations
5	C-Element Implementations Using Standard Cells 2-input C-Element’s Logic Function is: c = ab + c(a + b) = ab + bc + ac n-input C-Element is: c = a₁a₂…a_n + c(a₁ + a₂ + … + a_n) Thus may be implemented using two level logic or using an SR latch
6	C Gate Formal Models
7	Micropipeline Control Structure Req/Ack are handshaking pairs C[i] accepts 1/0 from C[i-1] only if C[i+1]=0/1 Think of 1010101.. as waves: ¹₀¹₀¹₀¹.. The C-elements propagate waves precisely Timing depends on local delays, may vary along the pipe If RIGHT is quiet, pipe will fill and stall Same for 4-phase, 2-phase
8	Micropipeline Analysis - PTnets Two-stage Micropipeline PTnet:
9	Micropipeline Analysis - PTnets Four-stage Micropipeline PTnet: Represents 4 C Elements and their environments Correct operation may be verified by possible signal orders
10	Micropipeline Analysis - PTnets Four-stage Micropipeline Ptnet Reduction to Latch Control Signals Characteristic Pattern:
11	Micropipeline Analysis - MSFSMs Two-stage Micropipeline FSMs: What about LHS/RHS FSM Interfaces? What are the two environment FSMs Rin/Ain, Rout/Aout?
12	Bundled-Data Concept Static combinational logic (typically) and standard FFs or latches Channels use bundled-data protocol Delay line matches worst-case delay of combinational logic Margin limits performance, particularly because adds to forward latency Controller CTRL drives local clock to bank of FFs (or latches) Designed using known templates or burst-mode controllers, signal-transition graphs, or syntax directed translation
13	Four-Phase Micropipeline Latches are active high Four-phase, so latches open on first ½ of h/s and close on second ½
14	Four-Phase Micropipeline Stage Four-phase protocol on Lreq/Lack and Rreq/Rack Latch is simple level sensitive traditional latch This is a half-buffer!
15	Four-Phase Micropipeline with C.L. Delay elements mimic worst-case critical path of Combinational Logic F of each pipe stage
16	Micropipeline 4-Phase PTnet including Latch Enable L Active-low in PTnet L- Opens L+ Closes Normally opposite
17	Two Phase Signaling
18	Capture-Pass Data Latch
19	Two-Phase Micropipeline Simple version without Cd (C done), Pd (P done) Little difference anyway in generating fake done signals (using delay elements)
20	Two-phase Micropipeline Stage – with CP Latches Store data upon Lreq event when last Pass event is done Ensure new store data only when old data is no longer needed Identified by right hand side changing Rack indicating does not need data Transition of Rack causes CP latch to go transparent Note two-phase protocol on Lreq/Lack and Rack/Req Full-buffer handshaking!
21	Two-phase Micropipeline Stage – with Transparent Latches Transparent Latches Much smaller than CP latch Level sensitive Thus, we need to convert two-phase control to four-phase XOR acts as a two-phase to four-phase converter Toggle acts as a four-phase to two-phase converter
22	Micropipeline 2-Phase PTnet including Latch Enable Multiple instantiations of L signal (L/1, 2)
23	Micropipeline 2-Phase PTnet including Latch Enable and Single Latch Signal Note the AC Return from Choice/Choice Needed
24	Two-phase Micropipeline Stage – with Double-Edge-Triggered FFs Efficient Double-Edge-Triggered FFs can also be used Buffer to FFs can be removed avoiding delay overhead
25	Delay Line Design Symmetric Designed with an even # of inverters that model worst-case path delay through combinational logic Asymmetric Faster reset implemented by replacing some INVs with NANDs Other May also use re-create path of gates along critical path to better match delay
26	Speculative Completion Sensing/Variable Latency Enables data-dependent component delays in bundled-data environment
27	Micropipeline Pitfalls