Synchronous FF Stage
}
Abstract synchronization
}
`SYNC(clk)
module
ff(clk, left, right)
input
clk;
input
left;
output
reg
right;
always
@(
posedge
clk)
begin
right = left;
end
endmodule
module
ff(clk, left, right)
input
clk;
input
left;
output
reg
right;
always
begin
`SYNC(
clk);
right = left;
end
endmodule
5
CE-653 - Handshake Channel Design