Logic
Hazards (Glitches)
CE-653 - Introduction and
Fundamentals
31
}Synchronous Circuits
}Glitches tolerated
because outputs sampled only after signals settle
}Clocking constraints
}Clock edge occurs only
after data
settles
settles
}Limits clock
frequency
}Asynchronous
Circuits
}Control circuits
}Avoided completely
}Hazard-free logic
synthesis techniques
}Datapath (Either)
}Outputs sampled after
signal settles OR
}Avoided completely