Synchronous
Design - Challenges
CE-653 - Introduction and
Fundamentals
29
}Design Complexity is
Increasing
}High frequencies depend on
careful pipelining
}Pipelining has algorithmic
implications
}Clock-stage misalignments
are a significant source of design error
}Reusing sub-circuits
depends on accommodating pipeline depth
}Mismatches may not
manifest under testing if critical data happens to hold constant
cycle-to-cycle
}Variation demands more
margin
}~30-40% lost to
process-corner (wafer) variation
}~5-10% lost to in-die
variation
}~10-20% lost to signal
integrity
}Standard discipline does
not accommodate multiple clocks easily
}Multiple clock-domains
challenging due to metastability issues
}Global clock-period must
enclose worse-case path
}Cost of doing business as usual is
increases ®
}Interest in alternatives
increases!