Baseline
Analysis
Semi-Custom Synchronous
Semi-Custom Synchronous
CE-653 - Introduction and
Fundamentals
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}Positives
ÉGood performance/power with 12-month
design times
ÉSupported by mature CAD tools
É Characterized cell
library
É Automated synthesis
from RTL
ÉMature physical design flows
}Negatives
−Use constrained circuits and methodology
−Static CMOS standard
gates
−Limited clocking and
gated-clocking methodologies
−Limited flip-flops with
large D-Q overheads
−Variation in deep-submicron
−Timing closure problems
causing schedule slips
−Variability causes large
margins in performance and power
−High electro-magnetic interference