Course Focus: Asynchronous VLSI Design
CE-653 - Introduction and
Fundamentals
2
}General Goal of Asynchronous VLSI Design
}Explore and take
advantage of more general circuit structures that do not have a single
global clock.
}CE653 Goal:
}Prepare engineers to
}Understand different async design styles and their tradeoffs
}Critically analyze their applicability
}Use existing asynchronous CAD tools
}Provide background for future study
}Goal of this lecture
}Why is asynchronous VLSI interesting?
}Put EE552 in context of USC VLSI & CAD Curriculum