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Basic VLSI
Overview
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Semi-conductor
Types: FPGA, ASIC, uProc, Memory Types
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Trends in VLSI
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Moore’s Law
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Increasing
variability
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Changing cost
functions
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Increasing
complexity, IP cores, SoC
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EDA Flows:
Full-Custom vs ASIC
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Synchronous vs
Asynchronous: Definitions
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Challenges of
Synchronous Design
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Clock
distribution, clock gating, clock power
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Costs due to
increasing variability
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At-speed testing
costs and impact
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Global
interconnect delays vs clock cycle
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Advantages of
Asynchronous
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(Top 10 reasons)
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Low Power,
High-Performance, Low EMI, GALS
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Cost of
Asynchronous
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Hazards
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Costs of
Hazard-Freedom
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Lack of CAD tools
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Recent
Commercialization Efforts
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Course goals
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Overview of
asynchronous logic
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Design styles
abound.
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Overview Papers
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PN, LP, Hazards
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Asynchronous
Architecture
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Tools (Cadence
Schematic + NC-Sim/Modelsim)
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More research than
industry
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