Βοηθητικό Υλικό
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Τα IWLS 1993 Benchmarks περιλαμβάνουν δειγματοληπτικά κυκλώματα τριών
ειδών: PLA, δηλαδή διεπίπεδη λογική σε μορφή κύβων, BLIF, πολυεπίπεδη
λογική σε μορφή δυαδικού δικτύου Boole, καί τέλος Μηχανές Πεπερασμένων
Καταστάσεων (FSMs) σε μορφή KISS, δηλαδή πίνακα κύβων.
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Σχετικές Δημοσιεύσεις (Εντός καί Πέραν της Ύλης του Μαθήματος)
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Δυαδικά Διαγράμματα Αποφάσεων - Binary Decision Diagrams (BDDs)
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Δυ-επίπεδη Λογική Σύνθεση
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Πολυ-επίπεδη Λογική Σύνθεση - Multi-Level Logic Synthesis
- R. K. Brayton, Factoring Logic Functions, IBM Journal on Research and Development, Vol. 31, No. 2, March 1987.
- Robert K. Brayton, Richard Rudell, Alberto Sangiovanni-Vincentelli, Albert R. Wang, MIS: A Multiple-Level Logic Optimization System, IEEE Transactions on Computer-Aided Design (CAD), Vol. CAD-6, No. 6, pp. 1062-1081 November 1987.
- R. K. Brayton, G. D. Hachtel, A. L. Sangiovanni-Vincentelli, Multilevel Logic Synthesis, Proceedings of the IEEE, Vol. 78, No. 2, February 1990.
- Ellen M. Sentovich, Kanwar Jit Singh, Luciano Lavagno, Cho Moon, Rajeev Murgai, Alexander Saldanha, Hamid Savoj, Paul R. Stephan, Robert K. Brayton, Alberto Sangiovanni-Vincentelli, SIS: A System for Sequential Logic Synthesis, ECL, Memorandum No. UCB/ERL M92/41, Department of Electrical Engineering and Computer Science, University of California, Berkeley, May 1992.
- Karen Bartlett, William Cohen, Aart de Geus, Gary Hachtel, Synthesis and Optimization of Multilevel Logic under Timing Constraints, IEEE Transactions on Computer-Aided Design (CAD), Vol. CAD-5, No. 4, pp. 582-596, October 1986.
- Kanwar Jit Singh, Albert R. Wang, Robert K. Brayton, Alberto Sangiovanni-Vincentelli, Timing Optimization of Combinational Logic, in Proceedings of IEEE International Conference on Computer-Aided Design (ICCAD), pp 282-285, 1988.
- Richard Rudell, Logic Synthesis for VLSI Design, Chapter 3, Algebraic Decomposition - Rectangle Covering, PhD Thesis, University of California, Berkeley, 1989.
- Alan Mishchenko, Roland Jiang, Satrajit Chatterjee, Robert Brayton, FRAIGs: Functionally Reduced AND-INV Graphs, Technical Report, Department of Electrical Engineering and Computer Science, University of California, Berkeley, 2005.
- Alan Mishchenko, Satrajit Chatterjee, Robert Brayton, DAG-Aware AIG Rewriting: A Fresh Look at Combinational Logic Synthesis, in Proceedings of the 43rd Design Automation Conference (DAC-2006), July 2006, San Francisco, California, USA.
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Πολυ-επίπεδη Λογική Σύνθεση - Multi-Level Logic Synthesis - DCs
Χ. Σωτηρίου - Tελευταία ενημέρωση - 9/10/2013.