# *******************************************************************************
# Vendor: Xilinx 
# Associated Filename: run_hls.tcl
# Purpose: Tcl commands to setup a Vivado HLS prject 
# Device: All 
# Revision History: March 1, 2013 - initial release
#                                                 
# *******************************************************************************
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##############################################
# Project settings

# Create a project
open_project	-reset matrixmul_prj

# The source file and test bench
add_files			matrixmul.cpp
add_files -tb	matrixmul_test.cpp
# Specify the top-level function for synthesis
set_top				matrixmul

###########################
# Solution settings

# Create solution1
open_solution -reset solution1

# Specify a Xilinx device and clock period
# - Do not specify a clock uncertainty (margin)
# - Let the  margin to default to 12.5% of clock period
set_part  {xc7k160tfbg484-1}
create_clock -period "75MHz"
#set_clock_uncertainty 1.25

# Simulate the C code 
csim_design
# Synthesize, Verify & Package IP
csynth_design
cosim_design
export_design


exit
