## ==============================================================
## File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
## Version: 2013.3
## Copyright (C) 2013 Xilinx Inc. All rights reserved.
## 
## ==============================================================

Starting export RTL ...
C:/Xilinx/Vivado_HLS/2013.1/Win_x86/bin/vivado_hls_bin.exe -flow export -flow_args " -format ip_catalog  -description \"An IP generated by Vivado HLS\" -vendor \"xilinx.com\" -library \"hls\" -version \"1.00.a\""
@I [LIC-101] Checked out feature [VIVADO_HLS]
@I [HLS-10] Running 'C:/Xilinx/Vivado_HLS/2013.1/Win_x86/bin/vivado_hls_bin.exe'
            for user 'duncanm' on host 'xsjduncanm-w7' (Windows NT_intel version 6.1) on Mon Apr 08 07:49:13 -0700 2013
            in directory 'C:/Vivado_HLS_Tutorial/Design_Analysis/lab1/dct_prj/solution6'
@I [IMPL-8] Exporting RTL as an IP in IP-XACT.
@I [IMPL-282] Generating Xilinx core: 'dct_mul_16s_15s_29_2_MAC2S_0'
@I [IMPL-282] Generating Xilinx core: 'dct_mul_16s_14ns_29_3_MAC3S_0'
@I [IMPL-282] Generating Xilinx core: 'dct_mul_16s_15s_29_3_MAC3S_1'
@I [IMPL-279] Implementing memory 'Loop_Row_DCT_Loop_proc_dct_coeff_table_0_rom' as auto ROMs.
@I [IMPL-279] Implementing memory 'Loop_Row_DCT_Loop_proc_dct_coeff_table_1_rom' as auto ROMs.
@I [IMPL-279] Implementing memory 'Loop_Row_DCT_Loop_proc_dct_coeff_table_2_rom' as auto ROMs.
@I [IMPL-279] Implementing memory 'Loop_Row_DCT_Loop_proc_dct_coeff_table_3_rom' as auto ROMs.
@I [IMPL-279] Implementing memory 'Loop_Row_DCT_Loop_proc_dct_coeff_table_4_rom' as auto ROMs.
@I [IMPL-279] Implementing memory 'Loop_Row_DCT_Loop_proc_dct_coeff_table_5_rom' as auto ROMs.
@I [IMPL-279] Implementing memory 'Loop_Row_DCT_Loop_proc_dct_coeff_table_6_rom' as auto ROMs.
@I [IMPL-279] Implementing memory 'Loop_Row_DCT_Loop_proc_dct_coeff_table_7_rom' as auto ROMs.
@I [IMPL-278] Implementing memory 'dct_buf_2d_in_0_memcore_ram' as block RAMs.
@I [IMPL-278] Implementing memory 'dct_row_outbuf_memcore_ram' as block RAMs.

****** Vivado v2013.1 (64-bit)
  **** Build 246863 by xbuild on Thu Mar 21 18:39:41 MDT 2013
    ** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.

INFO: [Common 17-81] Feature available: Implementation
INFO: [Common 17-81] Feature available: IPIntegrator_EA
INFO: [Common 17-81] Feature available: Synthesis
INFO: [Device 21-36] Loading parts and site information from C:/Xilinx/Vivado/2013.1/data/parts/arch.xml
Parsing RTL primitives file [C:/Xilinx/Vivado/2013.1/data/parts/xilinx/rtl/prims/rtl_prims.xml]
Finished parsing RTL primitives file [C:/Xilinx/Vivado/2013.1/data/parts/xilinx/rtl/prims/rtl_prims.xml]
INFO: [Common 17-362] Using Tcl App repository from 'C:/Xilinx/Vivado/2013.1/data/XilinxTclStore'.
INFO: [Common 17-364] Updating Tcl app persistent manifest 'C:/Users/duncanm/AppData/Roaming/Xilinx/Vivado/tclapp/manifest.tcl'
source run_ippack.tcl -notrace
INFO: [Common 17-206] Exiting Vivado at Mon Apr 08 07:49:38 2013...
@I [LIC-101] Checked in feature [VIVADO_HLS]


