# *******************************************************************************
# Vendor: Xilinx 
# Associated Filename: run_vhls.tcl
# Purpose: Tcl commands to setup Vivado HLS tutorial example
# Device: All 
# Revision History: March 31, 2013 - initial release
#                                                 
# *******************************************************************************
# Copyright (C) 2013 XILINX, Inc. 
# 
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# is protected under U.S. and international copyright and other intellectual 
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# 
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# ALL TIMES.

set run_frontend_prj 1
set run_backend_prj  1
set run_csim         1
set run_cosim        1

if { 1 } {
set part {xc7z020clg484-1}
set clk_period 6
} else {
set_part  {xc7k325tffg900-2}
set clk_period 4
}

# ****************************************************************************
# Frontend project
# ****************************************************************************
if { $run_frontend_prj } {
puts "\n# ****************************************************************************"
puts "# Frontend project"
puts "# ****************************************************************************\n"
   open_project fe_vhls_prj

   set_top hls_real2xfft

   add_files real2xfft.cpp
   add_files -tb xfft2real.cpp
   add_files -tb hls_realfft_test.cpp

   open_solution "IPXACTExport"
   set_part $part
   create_clock -period $clk_period

   config_rtl -reset_level low
   config_name -max_length 40

   if { $run_csim } {
      csim_design -clean
   }

   csynth_design
   if {$run_cosim} {
      cosim_design -trace_level all -rtl verilog
   }
   export_design
}

if { $run_backend_prj } {
puts "\n# ****************************************************************************"
puts "# Backend project"
puts "# ****************************************************************************\n"
   open_project be_vhls_prj

   set_top hls_xfft2real

   add_files xfft2real.cpp
   add_files -tb real2xfft.cpp
   add_files -tb hls_realfft_test.cpp

   open_solution "IPXACTExport"
   set_part  $part
   create_clock -period $clk_period

   config_rtl -reset_level low
   config_name -max_length 40

   if { !$run_frontend_prj && $run_csim } {
      csim_design -clean
   }

   csynth_design
   if {$run_cosim} {
      cosim_design -trace_level all -rtl verilog
   }
   export_design
}

exit

