// Top level CPU unit. This is where you instantiate and interconnect all modules
// in library.v and fsm.v

module cpu(input clock, input reset);
 reg [31:0] PC; 
 wire [31:0] instr, ALUInA, ALUInB, ALUOut, rdA, rdB, signExtend, wRegData, DMemOut, PCIncr;
 wire [3:0] ALUOp;
 wire Zero, RegDst, MemRead, MemWrite, MemToReg, ALUSrc, RegWrite, Branch, SeqOrJump;
 wire [5:0] opcode, func;
 wire [4:0] instr_rs, instr_rt, instr_rd;
 wire [4:0] wRegAddr;
 wire [15:0] imm;
 

 always @(posedge clock or negedge reset)
  begin 
// PC implementation. Do not forget the reset signal
  end
  
// Aliases
assign opcode = instr[31:26];
assign func = instr[5:0];
//   .....

assign wRegAddr = (RegDst==1'b0) ? instr_rt : instr_rd;
assign signExtend = {{16{imm[15]}}, imm};
// More assigns 

// MIPS ALU
ALU  #(.N(32)) cpu_alu(ALUOut, Zero, ALUInA, ALUInB, ALUOp);

// Register file


// Instruction memory 1KB

// Data memory 1KB

// Control Unit 


endmodule
