// Top level CPU unit. This is where you instantiate and interconnect all modules
// in library.v and fsm.v

module cpu (input clock, input reset);
 reg [31:0] PC; 
 reg IMemRead;
 wire [31:0] instr, ALUInA, ALUInB, ALUOut, rdA, rdB, wRegData, DMemOut;
 wire [3:0] ALUOp, RegWrite;
 wire [5:0] opcode, func;
 wire [4:0] instr_rs, instr_rt, instr_rd;
 wire [4:0] wAddr;
 

 always @(posedge clock or negedge reset)
  begin 
// Implement PC here. Do not forget the reset signal    
  end
  
assign opcode = instr[31:26];
assign func = instr[5:0];
// more assigns (aliases)

// assign wRegData = (MemToReg == 1'b0) ? ALUOut : DMemOut;

// MIPS ALU
ALU  #(.N(32)) cpu_alu(ALUOut, Zero, ALUInA, ALUInB, ALUOp);

// Register file
//

// Instruction memory 1KB


// Control Unit 
fsm cpu_fsm (RegWrite,
            ALUOp,
            opcode,
            func);
            

endmodule
